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Espressif Systems /ESP32-C2 /SYSTEM /BT_LPCK_DIV_FRAC

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Interpret as BT_LPCK_DIV_FRAC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BT_LPCK_DIV_B0BT_LPCK_DIV_A0 (LPCLK_SEL_RTC_SLOW)LPCLK_SEL_RTC_SLOW 0 (LPCLK_SEL_8M)LPCLK_SEL_8M 0 (LPCLK_SEL_XTAL)LPCLK_SEL_XTAL 0 (LPCLK_SEL_XTAL32K)LPCLK_SEL_XTAL32K 0 (LPCLK_RTC_EN)LPCLK_RTC_EN

Description

low power clock configuration register

Fields

BT_LPCK_DIV_B

This field is lower power clock frequent division factor b
BT_LPCK_DIV_A

This field is lower power clock frequent division factor a
LPCLK_SEL_RTC_SLOW

Set 1 to select rtc-slow clock as rtc low power clock
LPCLK_SEL_8M

Set 1 to select 8m clock as rtc low power clock
LPCLK_SEL_XTAL

Set 1 to select xtal clock as rtc low power clock
LPCLK_SEL_XTAL32K

Set 1 to select xtal32k clock as low power clock
LPCLK_RTC_EN

Set 1 to enable RTC low power clock

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data